TRACE32 Instruction Set Simulators

Highlights

• Integral part of TRACE32
• Configurable as system under debug (PBI=SIM)
• Allows post-mortem debugging
• Tool Qualification Support-Kit (TQSK) available for TriCore architecture
• Software compatible to all TRACE32 tools
• OS-aware debugging
• Cache simulation (architecture dependent)
• Program and data flow trace based on a bus trace protocol
• Advanced trace analysis features
• Powerful script language
• Programming interface for peripheral simulation
• Not available for processor architectures that support user-defined instructions

Support for AD, ALLWINNER, AMBIQMICRO, AMLOGIC, AMPERE, ANDES, ARDUINO, ARM, BROADCOM, CIRRUS, CLOUDBEAR, COBHAM, CODASIP, CORTINA, DIALOG, DIGI, FARADAY, FRAUNHOFER, GIGADEVICE, HILSCHER, HISILICON, IDT, INFINEON, INTEL, LAPIS, LSI, MACOM, MARVELL, MAXIM, MICROCHIP, MICROSEMI, NANOXPLORE, NORDICSEMI, NUCLEI, NUVOTON, NVIDIA, NXP, OKI, ONSEMI, QUALCOMM, RARITAN, RENESAS, RENESASSIEMENS, RISC-V, ROCKCHIP, SAMSUNG, SCALEOCHIP, SHARP, SIFIVE, SILICONLABS, SILICONMOBILITY, SOCIONEXT, STM, SYNTACORE, T-HEAD, TELECHIPS, TELEDYNE-E2V, TI, TOSHIBA, WESTERNDIGITAL, XILINX.

The TRACE32 Instruction Set Simulator is available for nearly all processor architectures supported by TRACE32. An intensive use of this tool requires a TRACE32 Simulator License.